Learning-Based Reconfiguration of Network-on-Chip for Varying Processing Requirements

• Main Authors: Jih-Sheng Shen, 沈日昇
• Other Authors: Pao-Ann Hsiung
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/21937933312113038317

博士 === 國立中正大學 === 資訊工程研究所 === 101 === Due to advanced process technologies, crosstalk interferences and high dynamic power consumption in a Network-on-Chip (NoC) are two increasingly problematic design issues. These problems become more severe in a NoC because of the large number of wires used for parallel communication. Using data codecs can reduce the switching activities on wires that cause crosstalk interferences and high dynamic power consumption. Nevertheless, these data codecs are usually not runtime customizable to application requirements, system characteristics, and user preferences. Further, there is a growing for systems to support more and more diverse applications. If a system needs to support new applications that demand more computing power than that provided by the current system, the time in market of the system is usually reduced. To adapt to the wide range of processing requirements including reliability, power efficiency, and functional flexibility, a novel flexible architecture, called Power-aware and Reliable Encoding Schemes Supported reconfigurable Network-on-Chip (PRESSNoC), is proposed in this Dissertation. PRESSNoC supports the dynamic hardware reconfiguration of processing elements (PEs), routers, and data codecs. For managing PE reconfiguration, a set of application program interfaces (APIs) is defined for the PRESSNoC architecture. For supporting router reconfiguration, a reconfiguration flow to prevent packet loss and related circuit designs are proposed. For meeting the requirements of reliability and power efficiency, a novel REasoning And Learning (REAL) framework is proposed that can make intelligent selections of data codecs. The key strategy used in the REAL framework to classify data codecs is the Artificial Neural Network (ANN). Tradeoffs among reliability degree, power reduction, performance overhead, and hardware resource usage are dynamically investigated so as to select an appropriate data codec that meets runtime requirements. As proof of concept, a prototype of the PRESSNoC with a 3×3 mesh topology was implemented on a Xilinx Virtex-4 FPGA device. Compared to a conventional NoC, it required 8.2% lesser number of slices. Compared to a baseline NoC that uses a fixed data codec, the average benefit to overhead ratio of the PRESSNoC is greater by 75.8%, 44.0%, and 186.8%, at the bit interference, application, and system levels, respectively. Experiments show that at the same overheads of performance and hardware resources PRESSNoC induces a higher probability toward the reduction of crosstalk interferences and dynamic power consumption. It also demonstrates the need for a dynamically reconfigurable NoC that supports hardware reconfiguration at runtime for different processing requirements.