A UHF RFID Tag SOC with ECG Acquisition for Intelligent Healthcare Systems

碩士 === 國立中正大學 === 電機工程研究所 === 101 === In this thesis, A wireless transceiver system for ECG acquisition has been implemented. We propose a novel method using Radio Frequency Identification(RFID) to detect the heartbeats of patients immediately. The target of our system is to achieve the purpose of l...

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Bibliographic Details
Main Authors: Lai Wei-Jhih, 賴韋志
Other Authors: Lee Shun-Yuh
Format: Others
Language:zh-TW
Published: 2013
Online Access:http://ndltd.ncl.edu.tw/handle/84426065000655864207
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Summary:碩士 === 國立中正大學 === 電機工程研究所 === 101 === In this thesis, A wireless transceiver system for ECG acquisition has been implemented. We propose a novel method using Radio Frequency Identification(RFID) to detect the heartbeats of patients immediately. The target of our system is to achieve the purpose of low-power, low-cost. The system chip is composed of four parts which are a RF-Front-End、a power management、a digital control and a analog-front-end(AFE). This thesis mainly consists of two parts of the RFID system. The first part is the RF front-end that contains a charge pump, an ASK demodulator, and a start-up circuit. The second part is the power management that covers a low-dropout regulator, a power-on-reset circuit, and a bandgap reference circuit. We propose the semi-passive RFID system to acquire ECG signals. First of all, the high-frequency signal is received by the antenna into the Tag. The RF-Front-End circuit would demodulate the 925Mhz carrier into digital signal. The start-up circuit is turned on at the same time, and the power circuit will supply the voltage to the RFID chip. Moreover, the POR would produce a pulse signal to reset all the logic circuits. After the system is turned on, the ECG signals is acquired by AFE instantly and the tag would transmit the signals to Reader by backscattering. The RF-Front-End and power management circuits are implemented in this thesis. The capacitor array and DDC(Distance-to-Digital) circuits are used to correct the error bit caused by the process variation and to solve the demodulation issue by limiter switches as the tag is too close to Reader. And the power circuit can also provide stable voltages to our chip. The overall circuit with core area of 0.965x0.965(mm2) has been implemented in TSMC 0.18μm 1P6M CMOS process technology. Measurement results show that the carier signal can normally be demodulated to digital core. In the future we will also make correction decoding algorithm integrated into the chip to handle the communication better.