|碩士 === 長庚大學 === 電子工程學系 === 101 === This thesis first part uses RF CMOS process to design the single-band 5.8GHz low voltage and low power consumption low-noise amplifier(LNA) with DC-current path-segmentation applications. 0.25um low noise amplifier has a gain about 11.5dB, noise of 3.3dB, the power consumption of 5.78 mW, and the chip area of 0.912x0.843 mm2.
The second part is designed for 3.1-10.6 GHz band of low noise amplifier. The low noise amplifier uses 0.18um RF CMOS Vanguard International Semiconductor module to achieve a noise canceling structure for 3.1 ~ 10.6 GHz frequency band. The simulated lowest power gain of 0.25um LNA is 12.4dB,and highest power gain is 15.3dB,and linearity P-1dB point between 24dBm and 17dB ,noise figure between 5.34dB and 5.19dB, power consumption of 22.4mW, circuit layout area is
The last part shows 3.1-10.6 GHz band of mixer and presents down-conversion mixer design using 0.18um RF CMOS Vanguard International Semiconductor module to achieve a noise canceling structure too. The simulated lowest power gain of 0.18um mixer is 15.35dB,and highest power gain is 16.46dB.The linearity of P-1dB point is between -20dBm and -17dB .The noise figure is between 11.65dB and 11.9dB.The power consumption is 22.9mW and circuit layout area is 0.73*1.352 mm2.