Design and Implementation of a 5GHz Frequency Synthesizer for Wireless Application

• Main Authors: YE,SHANG-LUN, 葉上綸
• Other Authors: Chi-Nan Chuang
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/96867983390964363376

碩士 === 華梵大學 === 電子工程學系碩士班 === 101 === In communication systems, whether it is wired or wireless hardware, you can find phase-locked loop. The traditional phase-locked loop (PLL) input reference frequency used quartz oscillator, and the frequency it provided was low; however, the high-speed quartz oscillator is more expensive than the general one so it’s not unfavorable for mass production. The level of reference signal affected the design of entire loop bandwidth. The level of loop bandwidth affected loop filter size, and also affected the overall lock time indirectly. Besides when designing the traditional PLL, must enlarge the range of input in VCO to overcome process variation. Controlling the limitation of voltage made VCO slope to be larger. Any small voltage disturbances in the control of voltage resulted in greater output jitter, while the smaller VCO slope was unable to overcome the process variation. The researcher proposed a new clock generator, using the delay locked loop to generate multi-phase output. By using edge combiner to multiply frequency to high speed and become phase-locked loop input reference signal, enhancing the frequency of reference input signal in phase-locked loop. It can enhance the loop bandwidth and reduce the required measure of area in the filter circuit. In the design of voltage-controlled oscillation, the researcher used the design of multi-band in VCO to achieve low slope and overcome process variations in voltage-controlled oscillator. This thesis used TSMC 0.18um 1P6M 1.8V CMOS to achieve the process. Chip size is 1.2*1.2mm2 . The reference frequency is 25MHz. The output frequency is 5GHz. The power consumption is 20.3mW.