| Summary: | 碩士 === 華梵大學 === 電子工程學系碩士班 === 101 === Delay locked loop commonly used in the phase snchronization,
Frequency multiplier and multi-phase generation. Compared to the phase locked loop .The advantages are small size,lock speed, can produce multi-phase bound stable. However delay locked loop limited harmonic lock,false lock problems and limited range of voltage controlled delay lines,restrict the range of the input signal operation.
In this thesis proposes a new voltage-controlled delay line, change the traditional architecture,Enhance the operational range of the input signal. Traditional simple Voltage-Controlled Delay Line(vcdl) from the inverter variable and capacitors, if you have using wide rang operating , you need to use switching variable capacitance, wide rang operating can be achieve ,However if using duty cycle to phase delay cell(DTP) Composition Voltage-Controlled Delay Line, Be able to resolve Traditional architecture using variable capacitance, Reduce phase errors caused by the delay
In delay locked loop based on the design of a 360 phase voltage control delay Line, Eight voltage control lines, replacing traditional single control line voltage.In addition to eight by the input signal through the circuit generates eight phases as eight loop input signal and reduce multi-stage delay units cascaded noise caused by accumulation, increased jitter and phase mismatch problems.
In this thesis, using TSMC 0.18um 1P6M 1.8V CMOS made implementation. Chip size 1.2*1.2mm2, the reference frequency 22~625MHz,, the output frequency of 22~625MHz, Output phase is eight phase ,the power consumption is 100mW.
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