A Low Voltage GFSK Demodulator Design for Buletooth Wireless Communication Applications

• Main Authors: Tsao, Yi-Po, 曹軼博
• Other Authors: Fang, Jen-Chun
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/72588218132529138857

碩士 === 龍華科技大學 === 電子工程系碩士班 === 101 === This thesis introduces the base band circuit design processing by the TSMC 0.18μm CMOS technique. The main research objective is the design of demodulator, First, by the input signal is amplified a limiting amplifier flowing, through a low-pass filter, the signal is feed into the quadricorrelator. Then the quadrature signal are combined with cross coupled multipliers to perform demodulation.All the circuit stages, appling low voltage of 0.6V, use cascaded gain stages. Besides, Sallen-key architecture is used as low-pass filter, for reducing cost of wireless communication system and improving performance,as well as smailer size and lower power cinsumption. The chip measurement results, use the supply voltage of 0.6V, IF is 2MHz, Data rate of 0.4MHz and 0.1MHz, total current of 6.13mA, total power consumption is 3.68mW circuit.The chip size including pads is 2.23×2.23mm.