| Summary: | 碩士 === 龍華科技大學 === 電子工程系碩士班 === 101 === This thesis introduces the RF circuit design processing by the TSMC 0.18μm CMOS technique. The main research objective is the front-end circuits of QPSK transmitter, which contains a low power VCO, Current-bleeding technique and third-order intermodulation distortion cancellation technique, a linearity improving power amplifier, a low power up-conversion self-oscillating mixer.
The first chip is “A Low Power 5.8GHz OOK Transmitter Design using swiched VCO Technology”. A Low Power OOK transmitter using TSMC 0.18μm CMOS technology for IEEE 802.11a application is proposed in this design. Measurement results of the proposed OOK transmitter exhibits the output power of -11.41dBm, tuning range of 5.255~5.44GHz and phase noise of -87.064dBm while consuming 2.44mW from a 1.2V supply voltage. The chip size including pads is 1.4×0.89mm2.
The second chip is “Design of Up-Conversion Mixer with Low Power Consumption VCO”. The measured results of the proposed mixer reveal a conversion gain of -28.44dB, input third-order intercept (IIP3) of -25.81dBm and tuning range of 4.687~5.48GHz. The power consumptions are 1.96mW for the VCO and 7.16mW for the mixer. The size of the chip is 1.644x 1.05 mm2.
The third chip is “An RF Power Amplifier Design for ISM Application”. The measured results of the designed chip exhibit the power gain of 22.321dB, input third-order intercept (IIP3) of 1.57dBm, OIP3 of 22.32dBm and output power of 16.18dBm. The power consumptions 3.08mW for the linearizer and 242.2mW for the driver stage and power stage. The PAE level of this PA is 16.95%. The size of the chip is 1.644 x 1.05mm2.
The fourth chip is “A RF Front-end Circuit Design of Transmitter for ISM Application”. The designed front-end circuit comprises PA, VCO, and Mixer. The proposed third-order intermodulation distortion cancellation mixer can achieve high linearity and high gain performances. When integrated in a 0.18 μm CMOS technology, the front-end circuit exhibits an area of 1.537x 2 mm2. The proposed front-end circuit achieves simulated power gain of 28.219dB, input third-order intercept point (IIP3) of 0.23 dBm, output power of 14.339 dBm, VCO tuning range of 4.795~5.231 GHz and phase noise of -117.269 dBc/Hz at 1-MHz offset frequency under total consuming power of 165.39 mW from 2.8V supply voltage.
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