FFT and Soft-output MIMO signal Detector IP designs for OFDM communication systems

• Main Authors: Yi-You Chen, 陳怡佑
• Other Authors: Yin-Tsung Hwang
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/40826295245064425653

碩士 === 國立中興大學 === 電機工程學系所 === 101 === This thesis deals with the application of Orthogonal Frequency Division Multiplexing (OFDM) scheme in the optic fiber-to-the-home communications and Multi-input Multi-output (MIMO) communication systems. We first investigate on the design of a real-valued Fast Fourier Transform (RFFT) with high-speed 64 points in the fiber-optic communication system. The conjugate characteristic of the algorithm is utilized to reduce the computing complexity. Changing the complex-valued operation into real-valued in each stage can not only reduce the operational complexity but also make each stage operating on the same throughput. The sample frequency of RFFT is 2GHz to comply with the sampling rate. In this thesis, the design is eight-way parallel and the system working frequency are set the 250MHz. We next investigation on the design of a soft-output detector in the 4x4 64-QAM MIMO system. The Search Process in the K-best algorithm is employed to seek through every stage for the minimum error and the maximum PED of each bit as the information. A total of four types of soft-output algorithm, i.e. , One Pass LLR, Progressive update LLR, Final stage updata LLR-1, and the Final stage updata LLR-2 are developed. A Combinative Enumeration scheme is adopted in this thesis to reduce the loading of sort circuit and node computation. To further enhance the efficiency of sorting scheme and to lower the utility rate of Comparator, a Simplified Parallel Bubble-Slice Sorter was designed. Simply, Shift Multipliers are used to replace the Conventional Multiplier for lower hardware complexity. From the simulation results, we find that when the Bit Error Rate (BER) is significantly around 10-3, the real-valued Fast Fourier Transform can reduce the computing complexity. While the performance loss only 0.4dB when compared with conventional real-valued FFT design. To proposed FFT designs are realized using Xilinx''s Virtex 5 LTX validation platform with high speed RocketIO links. The implementation results show that the design can operate ate 251.3MHz and the effective sample frequency can reach 2.01GHz.For sort-output MIMO detector design, the application of K-best algorithm with K=8 and boundary=±32. The implementation results show that the design can operate ate 120MHz and the throughput can reach 720Mbps.