| Summary: | 碩士 === 國立中興大學 === 電機工程學系所 === 101 === The paper describes the design and realization of a quadracture voltage-controlled oscillator (QVCO), a frequency doubler (FD) and a high-speed frequency divider for a 60-GHz RF frequency synthesizer that has been implemented with 90nm CMOS technology. The FD provides the tuning range of 46.8 to 48.8 GHz (4.18%). At 48GHz carried frequency with doubling-frequency operation, the simulated phase noise is -95.71 dBc/Hz at 1-MHz offset. Simultaneously, the fundamental frequency output by the QVCO provides the phase noise of -96.01dBc/Hz at 1-MHz offset. The core circuit dissipates below 55mW at a 1.2V supply.
This paper is divided into three parts, first introduced the concept of phase-locked loop , and research motivation and norms, especially the part 60GHz''s application will be particularly described.
Then will do the various sub-circuit analysis and simulation, especially QVCO part explains how to analyze and design of low noise, and pulse swallow counter part, explains how to design divide high-frequency, low power consumption and high resolution, and use current reusing doubler and let its symmetry to reduce noise.
Last part of the consideration for wafer measurements, as well as explain the difference between the software, and parasitic effects assessment to do commentary, and improvement for future research topics can be discussed.
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