| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 101 === This thesis proposes a novel single-phase seven-level inverter, which produce three levels of voltage variations, hence the seven-level output is achieved. The proposed inverter uses only one DC source and two capacitors. The time period of energy storing and releasing are identical in one switching cycle, Thus capacitor voltage is balanced without voltage-balancing circuit. This is a distinct advantage in comparison with other conventional seven-level structures, which often use three or more capacitors that lead to voltage-unbalancing of capacitors. Simple control strategy is adopted.
The proposed topology has the advantage of low voltage harmonic distortion, absence of voltage-balancing circuit, less input capacitors, smaller low pass filter size, and low switch voltage stress.Experimental results obtained from a 360 V input voltage, 380 Vrms output voltage, and 3 kW output power prototype circuit was presented to verify the system performance.
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