| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 101 === In this thesis, a 12-bit 2GS/s current-steering DAC design is presented to overcome the three main nonlinearity sources, which are current source mismatch, output transition nonlinearity, and finite output impedance, and achieve high-speed high-resolution characteristic. Firstly, for the current source mismatch, two different dynamic element matching (DEM) algorithms, random rotation-based binary-weighted selection (RRBS) and data weighted averaging (DWA), are adopted to process the harmonic distortion tones caused by mismatch error for different applications. Secondly, reduced-switch and non-cascoded modifications of the current cells increase the output transition speed and decrease the influence of transition nonlinearity. In addition, a digital resetting return-to-zero (RTZ) is adopted to further enhance the output transition linearity. Finally, for the finite output impedance, an output impedance compensation circuit is proposed to compensate the nonlinear impedance curve of current cells. By dealing with these nonlinearity sources, this DAC performs excellent at high sampling rate.
The current-steering DAC is fabricated in TSMC 90nm 1P9M CMOS technology with only 0.07mm2 of active area. The measurement results show that the DAC achieves 〉70dB SFDR from dc to 400MHz sampling at 1GHz and performs best in figure of merit (FOM) comparing to state-of-the-art works.
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