High Speed Speaker Recognition Chip Design Based on Switchable Butterfly Architecture

• Main Authors: Hong-YuanPeng, 彭泓元
• Other Authors: Jhing-Fa Wang
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/58384073108351369053

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 101 === This paper proposed an application-specific integrated circuit (ASIC) architecture for speaker recognition. There are three parts of this proposed system, which is including: feature extraction module, training module, and recognition module. LPCC (Linear Predictive Cepstral Coefficients) is adopted into the proposed feature extraction module. As the characteristics of symmetrical and periodical data transmission, we design a switchable butterfly architecture to optimize the efficiency of data accessing. Moreover, this module employs the reusable mechanism to perform two modes for achieving high speed and low chip area requirement. Reconfigurable hardware design for sequential minimal optimization (SMO) is applied in the proposed training module. Overall, this training module is a parallel-mesh architecture which contains 16 processing elements (PEs).We can switch the proposed training module into different mode by changing the datapath to speed up various training tasks. The last part of the proposed ASIC architecture is recognition module which is utilized Support Vector Machine (SVM) algorithm as classifier. For SVM, we design a voting analysis circuit so that we can achieve multi-class speaker recognition demand. The proposed design has been send to National Applied Research Laboratories (NAR Labs), and be manufactured by Taiwan Semiconductor Manufacturing Company Limited (TSMC).