High Speed Speaker Recognition Chip Design Based on Switchable Butterfly Architecture

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 101 === This paper proposed an application-specific integrated circuit (ASIC) architecture for speaker recognition. There are three parts of this proposed system, which is including: feature extraction module, training module, and recognition module. LPCC (Linear Pre...

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Bibliographic Details
Main Authors: Hong-YuanPeng, 彭泓元
Other Authors: Jhing-Fa Wang
Format: Others
Language:en_US
Published: 2013
Online Access:http://ndltd.ncl.edu.tw/handle/58384073108351369053

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