Embedded Debugging Architecture of Bug Detection and Reproduction for SoC Post-Silicon Validation

• Main Authors: Chen, Shing-Yu, 陳星諭
• Other Authors: Chen, Tien-Fu
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/05837690339309227805

碩士 === 國立交通大學 === 資訊科學與工程研究所 === 101 === As digital devices and system on chip (SoC) are becoming prevalent in recent years, post-silicon validation has been indispensable for SoC designs. In SoC designs, it is crucial to test the design correctness for product success. However, the complexity of modern SoC designs keep increasing, it is difficult to cover all behaviors in manufactured chip by existing validation techniques. Therefore, post-silicon validation is a major challenge for future systems. This work proposes an embedded debugging architecture for bug detection and reproduction during post-silicon validation. In the debugging system, system-level bugs are detected in real-time for accurately localizing bugs. In addition, by using the timestamp mechanism provided by the debugging system, the tested system is capable of reproducing bugs for cyclic debugging. Further, the storage and bug reproduction overhead are significantly reduced by using special post-analysis techniques. The experimental results show that the debugging system improves (1) debugging execution time > 80%, (2) storage overhead 49% ~ 56% and bug reproducing overhead ~46%.