| Summary: | 博士 === 國立交通大學 === 資訊科學與工程研究所 === 101 === In this dissertation, two energy-efficient signal separation systems are explored and implemented. Energy-efficient VLSI signal processing design can be achieved by reducing computational complexity in the algorithm level. Many computational complexity reduction schemes are proposed for two signal separation systems, and the corresponding VLSI architectures are implemented to show the energy efficiency.
In nonblind signal separation system, considering spatial multiplexing MIMO detection system under flat fading channel, an energy-efficient multimode multiple-input multiple-output (MIMO) detector using a modified adaptive list length scheme is presented. The list length is selected according to the channel condition to reduce computational complexity. The proposed MIMO detector supports 2×2/4×2/4×4 antenna numbers with QPSK/16-QAM/64-QAM inputs and possesses low complexity with satisfactory bit error rate (BER) performance. In terms of architecture, we propose a region-partition-based multiple-symbol selection (RPMSS) architecture with a modified adaptive list length selection (MALLS) unit to lower the power, a scalable tree search with PED calculation (STSPC) unit and a scalable parallel-pipeline sorting network (SPPSN) architecture to enhance the throughput of the MIMO detector. The resulting MIMO detector in TSMC 0.18 μm 1P6M CMOS process possesses maximum throughput of 1,284 Mbps and core area of 2.56 mm2 with 210 K gates. The power dissipation of the 4×4 MIMO system with 64-QAM inputs is 282.6 mW@107 MHz at 1.8V, and the resulting energy efficiency is 220.1 pJ/bit. Moreover, compared with the design without the modified adaptive list length scheme, the proposed MIMO detector achieves power reduction by 45.49% with loss of 0.1 dB.
In blind signal separation system, considering electroencephalogram (EEG) signal separation system using independent component analysis (ICA), an energy-efficient fast independent component analysis (FastICA) implementation with an early termination scheme for eight-channel EEG signal separation is presented. The main contributions are as follows. 1) Energy-efficient FastICA architecture using the proposed early termination scheme; 2) cost-effective FastICA using the proposed preprocessing unit architecture with one CORDIC-based eigenvalue decomposition (EVD) processor and the proposed one-unit architecture with the hardware reuse scheme; 3) low-computation-time FastICA using the four parallel one-units architecture. The resulting power dissipation of the FastICA implementation for eight-channel EEG signal separation is 16.35mW@100MHz at 1.0V. Compared with the design without early termination, the proposed FastICA architecture implemented in UMC 90nm 1P9M CMOS process with a core area of 1.221×1.218 mm2 can achieve average energy reduction by 47.63%. From the post-layout simulation results, the maximum computation time is 0.29 second.
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