Investigation and Analysis of FinFET and Trigate Devices, Logic and Analog Circuits, and SRAM

• Main Authors: Pao, Chia-Hao, 包家豪
• Other Authors: Chuang, Ching-Te
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/66372196298044298147

碩士 === 國立交通大學 === 電子研究所 === 101 === In this thesis, we present a comprehensive comparative analysis of FinFET and Trigate in terms of device characteristics, stability of 6T SRAM cell, logic circuits and Widlar current source. The critical intrinsic random variations, including fin Line Edge Roughness (fin LER), Work Function Variation (WFV) and single-trap-induced Random Telegraph Noise (RTN) on FinFET and Trigate devices are investigated and compared using 3D TCAD atomistic simulations. The results indicate that Trigate device shows slightly better variability immunity in Subthreshold Slope (S.S.), threshold voltage (VT), 6T SRAM cell stability with identical electrical width and fin width (10nm and 7nm) considering fin LER and WFV simultaneously. While considering the impact of RTN, Trigate device, with larger fraction of electron current near the bottom region of the silicon fin channel, suffers larger RTN degradation for the trap located at the bottom region, whereas less impact is observed with single charged trap at the top region. As such, Trigate device exhibits broader dispersion and stronger dependence on the trap location. In the presence of fin LER and WFV, larger impact is found in RTN amplitude (ΔID/ID), nominal Δgm/gm, σ(Δgm/gm) and ΔVT with a trap placed at the worst position of Trigate MOSFET. Furthermore, the influence of RTN on 6T SRAM cell stability, Widlar current source, the leakage-delay of inverter, Two-Way NAND and 2-To-1 Multiplexer (MUX) are examined. It is observed that with degreasing supply voltage, the importance of RTN degradation increases, and that Trigate-based circuits are found to be inferior to the FinFET counterparts.