| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 101 === Static Random Access Memory (SRAM) plays an important role in the System on Chip (SOC) design. Because of the large process variation in the advanced process and the small Ion/Ioff ratio at low voltage, the traditional 6T and 8T SRAM can’t work when operating at low voltage.
In the thesis, first, a new bit-interleaving 11T subthreshold SRAM cell with Data-Aware-Power-Cutoff (DAPC) Write-assist is proposed to mitigate the Write-ability problem caused by the process variation and bit-interleaving structure. Measurement results of a 4Kb test chip implemented in 40nm General Purpose (40GP) CMOS technology shows that VDD can down to 0.32V (~0.69X of threshold voltage) with operation speed of 3.5MHz with VMIN limited by Read operation. And the Write VMIN is 0.31V.
Second, a new Data-Aware-Power-Cutoff 12T SRAM cell is proposed to solve the column-half-select-data-retention problem which happens during Write operation in the previous 11T SRAM cells. Because of the compact and symmetric layout style, the cell area of this 12T cell is smaller than previous 11T cell by 4%. According to the 20000 times Monte-Carlo simulation in 40GP, the Hold ability and Write ability of this 12T cell are very reliable. The error rate is 0.025% with the VDD down to 0.25V. After solving the Write problem by the 12T cell, a Pattern-Aware-Keeper is proposed to solve the Read problem caused by the accumulation of leakage of unselected cells in the long bit line condition. The Pattern-Aware-Keeper and 12T cell are implemented as a 8Kb (64X128) SRAM in 40nm General Purpose (40GP) CMOS technology. In the simulation with random local variation, this 8Kb 12T SRAM is fully functional at 0.28V with the operation speed of 3.3MHz, and the VMIN is limited by Read operation. Because the long bit line structure can reduce the area of peripheral circuit, the total area is 14614 um2 (253.535um ? 57.64um) and the area per bit is just 1.785 um2 in this 8Kb 12T SRAM.
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