| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 101 === In wireless communication system, channel coding modules play an important role. For providing a highly competitive solution, both high throughput transmission and low power consumption are required. Due to the capacity-approaching performance and inherent parallel architecture, LDPC block codes have attracted great interests in recent years. However, the problem of high routing complexity is a serious design challenge in VLSI implementations. Moreover, the complexity of designing multiple code-rates LDPC block codes is increased since dedicated parity-check matrices are needed to be jointly considered. Developed in 1999, LDPC convolutional codes are capable of handling arbitrary data frame length and possess flexible code-rates through puncturing. While performing the capacity-approaching performance, the routing complexity of the convolutional version is much lower than that of the LDPC block code's.
For real applications, however, tail-biting scheme or termination sequence should be employed. To avoid the code-rate loss, a LDPC convolutional code which can have the tail-bitten version is constructed in our work. Besides, a memory-based architecture is adopted to save the power consumption. Scheduling optimization which enhances both the performance and throughput is also provided in our design. Fabricated in UMC 90nm 1P9M CMOS process, the proposed TB-LDPC-CC decoder chip could achieve 1.83 Gb/s throughput under 305 MHz operating frequency with 0.8V supply voltage at 4 decoding iterations. The total core area is 2.27 mm^2 with 90.2% chip utilization.
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