DESIGN AND IMPLEMENTATION OF ESD PROTECTION CIRCUITS IN NANOSCALE FULLY SILICIDED CMOS TECHNOLOGY

• Main Authors: Yeh, Chih-Ting, 葉致廷
• Other Authors: Ker, Ming-Dou
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/21516069672622673780

博士 === 國立交通大學 === 電子研究所 === 101 === As CMOS technology is continuously scaled down to nanoscale, the gate oxide becomes thinner and the diffusion junction depth becomes shallower. These lead to the reduced gate oxide breakdown voltage and increased gate leakage current of MOS transistor. The reduced gate oxide breakdown voltage makes the MOS transistor more vulnerable to electrostatic discharge (ESD) because ESD is not scaled down with the CMOS technology. The gate leakage current makes the MOS transistors in ESD protection circuit malfunction during ESD stresses and normal circuit operating condition. ESD is one of the most important reliability issues for the integrated circuit (IC) during mass production. It must be taken into consideration during the design phase to meet the reliability specifications for all microelectronic products. For whole-chip ESD protection design, all pads, including the input/output (I/O) pads and VDD/VSS pads, are necessary to be implemented with ESD protection circuits to provide effective ESD protection for the IC. The ESD protection devices between the I/O pads and VDD/VSS pads inevitably cause parasitic effects on the signal path of RF front-end and high-speed circuits, which are very sensitive to those parasitic effects. The challenge of ESD protection devices for RF front-end and high-speed circuits is to sustain the highest ESD level and to achieve the smallest parasitic effects. Moreover, the ESD protection circuits between the VDD/VSS pads are necessary to provide ESD protection between the power rails. Although the parasitic effects of power-rail ESD clamp circuit have no impact on the internal circuits, the reduced gate oxide breakdown voltage and increased gate leakage current of MOS transistor greatly increase the difficulty of ESD protection design. In addition, the fabricated cost per unit area of the IC is dramatically increased with the continuously scaled-down CMOS technology. Therefore, the power-rail ESD clamp circuit with high efficiency of layout area is another design challenge. The research topics based on aforementioned design challenges in this dissertation including: (1) ESD protection diode for RF and high-speed I/O applications, (2) capacitor-less power-rail ESD clamp circuit, (3) power-rail ESD clamp circuit with equivalent ESD-transient detection mechanism, (4) power-rail ESD clamp circuit with considerations of gate leakage current and gate oxide reliability, and (5) resistor-less power-rail ESD clamp circuit. In Chapter 2, new ESD protection diodes drawn in the octagon, waffle-hollow, octagon-hollow, multi-waffle, and multi-waffle-hollow layout styles are presented in a 90nm CMOS process. The experimental results confirmed that they can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the stripe and waffle diodes. Therefore, the signal degradation of RF and high-speed transmission can be reduced. In Chapter 3, a new ESD-transient detection circuit without using the capacitor has been proposed and verified in a 65nm 1.2V CMOS process. The layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%, as compared to the traditional RC-based one. The new ESD-transient detection circuit with adjustable holding voltage has better immunity against mis-trigger and transient-induced latch-on event under the fast power-on and transient noise conditions. In Chapter 4, a power-rail ESD clamp circuit realized with ESD clamp device drawn in the layout style of BigFET, and with parasitic diode of BigFET, is proposed and verified in a 65nm 1.2V CMOS process. Utilizing the diode-connected MOS transistor as the equivalent large resistor and parasitic reverse-biased diodes of BigFET as the equivalent capacitors, the new RC-based and capacitance-coupling ESD-transient detection mechanism can be achieved without using an actual resistor and capacitor to significantly reduce the layout area by ~82%, as compared to the traditional RC-based ESD-transient detection circuit. In Chapter 5, a power-rail ESD clamp circuit realized with only thin gate oxide devices and with SCR as main ESD clamp device has been proposed and verified in a 65nm 1V CMOS process. By reducing the voltage difference across the gate oxide of the devices in the ESD-transient detection circuit, the proposed design can achieve a low standby leakage current. In addition, the ESD-transient detection circuit can be totally embedded in the SCR device by modifying the layout structure. In this chapter, a 2×VDD-tolerant power-rail ESD clamp circuit has also been proposed and verified in the same CMOS process. The proposed design with SCR width of 50□m can achieve a low standby leakage current of 34.1nA at room temperature under the normal circuit operating condition with 1.8V bias. In Chapter 6, a resistor-less power-rail ESD clamp circuit realized with only thin gate oxide devices, and with SCR as main ESD clamp device, has been proposed and verified in a 65nm 1V CMOS process. Skillfully utilizing the gate leakage current to realize the equivalent resistor, the RC-based ESD-transient detection mechanism can be achieved without using an actual resistor. The resistor-less power-rail ESD clamp circuit with SCR width of 45□m can achieve an ultra-low standby leakage current of 1.43nA at room temperature under the normal circuit operating condition with 1V bias. In this dissertation, several novel designs have been proposed in the aforementioned research topics. Measured results of the fabricated test chips have demonstrated the performance improvement. The innovative designs and achievements of this dissertation have been published or submitted to several international journals and conferences.