DESIGN AND IMPLEMENTATION OF ESD PROTECTION CIRCUITS IN NANOSCALE FULLY SILICIDED CMOS TECHNOLOGY
博士 === 國立交通大學 === 電子研究所 === 101 === As CMOS technology is continuously scaled down to nanoscale, the gate oxide becomes thinner and the diffusion junction depth becomes shallower. These lead to the reduced gate oxide breakdown voltage and increased gate leakage current of MOS transistor. The reduced...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2013
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/21516069672622673780 |