Area-Power-Efficient 11-Bit SAR ADC with Delay-Line Enhanced Tuning for Neural Sensing Applications

• Main Authors: Huang, Teng-Chieh, 黃騰頡
• Other Authors: Chuang, Ching-Te
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/56653870857500181759

碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 101 === In a bio-signal acquisition system for high-density neural sensing applications, the occupied area and power consumption are two critical challenges for the neural recoding circuits consisting of recording amplifiers, analog-to-digital converters (ADCs) and digital processing circuits. In view of this, an area-power-efficient 11-bit hybrid ADC with delay-line enhanced tuning is presented for neural sensing applications in this thesis. Furthermore, a 16-channel neural recording system with 4 hybrid ADCs is implemented in a 2.5D heterogeneous integration. For reducing the total amount of capacitance, the proposed hybrid ADC is composed of a course tune and a fine tune by 3-bit delay-lined-based ADC and 8-bit successive approximation register (SAR) ADC, respectively. The delay-lined-based ADC is designed to detector the three MSBs by a voltage-to-time converter and a modified vernier time-to-digital converter. To relax the accuracy requirement of the coarse tune, the lifting-based searching algorithm and re-comparison procedure are proposed for the fine tune. In addition to further achieve energy saving, split capacitor array and self-timed control are utilized in the SAR ADC. Fabricated in UMC 180nm CMOS technology, an ENOB of 10.4-bit at 32KS/s can be achieved. Furthermore, the power consumption and area occupation are only 2.24μW and 0.032mm2, respectively. The FoM of the proposed hybrid ADC with delay-line enhanced tuning is 49.16fJ/conversion-step.