VLSI Implementation of a Compressed Sensing Recovery
碩士 === 國立交通大學 === 電控工程研究所 === 101 === This paper proposes two recovery algorithms modified from subspace pursuit(SP) for compressed sensing problems. The two algorithms can reduce the complexity of SP and maintain the high recovery rate. Complexity analysis and simulation results are provided for th...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/tt9739 |
| Summary: | 碩士 === 國立交通大學 === 電控工程研究所 === 101 === This paper proposes two recovery algorithms modified from subspace pursuit(SP)
for compressed sensing problems. The two algorithms can reduce the complexity of
SP and maintain the high recovery rate. Complexity analysis and simulation results
are provided for the proposed algorithms and other conventional recovering
algorithms. We observe that the proposed algorithms can perform well. Besides, this
paper also proposes an architecture for one of the proposed recovering algorithm for
VLSI implementation. Several hardware units are dedicated designs for the
implementation. The proposed chip is implemented using a TSMC 90nm process and
can use a clock rate of 100MHz with total area is 11.69 mm2. The average power is
431mW.
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