Design of Reconfigurable High Speed SVD Processor

• Main Authors: Hsin-Chang Chen, 陳信彰
• Other Authors: Muh-Tian Shiue
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/70483338489726939029

碩士 === 國立中央大學 === 電機工程學系 === 101 === In recent years, it is more important to use MIMO (Multi-Input Multi-Output) systems. MIMO techniques not only increase system throughput but also improve system performance such as BER (Bit Error Rate). Due to different configurations of antennas between transmitter and receiver, there are a few issues to be solved. SVD (Singular Value Decomposition) is a common used precoding technique for beamforming, and as the design target of implementation in this thesis. This thesis proposes a reconfigurable architecture which can compute the SVD of 1 × 1~4 × 4 antenna configurations’ channel matrices. For reducing the clock delay lead of conventional memory-based architecture, this thesis employs register arrays to replace the real memory, and implements the GR-SVD algorithm by a pipelined circuit design. The design results improve not only on throughput, but also the advantages of low power and small area in chip implementation. The proposed configurable SVD processor is function-verified by the SIMIS VeriEnterprise Xilinx FPGA development board. Besides, the proposed architecture is also implemented in TSMC-90nm for demonstrating the achievement of throughput, low power and small area.