The Low Voltage RF Front-end in 0.18 um CMOS for Wireless Communication Systems

碩士 === 國立東華大學 === 電機工程學系 === 101 === In recent years, CMOS process satisfies the requirement of low voltage, low power, compact size, and high integration in RF circuit design. The low power and high integration RF receivers are the trends for high data transmission rate wireless communication sys...

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Bibliographic Details
Main Authors: Ming-Jhe Zeng, 曾銘哲
Other Authors: Ro-Min Weng
Format: Others
Published: 2013
Online Access:http://ndltd.ncl.edu.tw/handle/13252270196599265693
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Summary:碩士 === 國立東華大學 === 電機工程學系 === 101 === In recent years, CMOS process satisfies the requirement of low voltage, low power, compact size, and high integration in RF circuit design. The low power and high integration RF receivers are the trends for high data transmission rate wireless communication systems due to the demand of portability and the limitation of battery capacity. In this thesis, there are four RF sub-circuits implemented by tsmc 0.18-um CMOS technology with a supply voltage of 0.8 V for ultra-wideband (UWB) and global positioning system (GPS) applications. First, a low power folded subharmonic mixer for UWB upper-band systems is presented. The operation frequency range is from 6 to 10.6 GHz. In order to lower the supply voltage, the folded structure is used. The local oscillation frequency doubler can half the frequency of the input LO signal. The output amplitude can be enhanced to increase the conversion gain of the mixer. However, there is a drawback of high noise. Intermediate frequency is kept at 100 MHz during measurement. Hence, only LO frequency range from 2.95 GHz to 5.25 GHz is required. The measured conversion gain is 5.4±3.1 dB and the maximum P1dB is -10.5 dBm. IIP3 is -6 dBm at 8 GHz. The average noise figure is 15 dB within the operating frequency. The LO-to-RF and LO-to-IF isolations are better than 60 dB. The power consumption is 4.3 mW. The chip size is 0.99 mm2. Second, a 3.95 GHz enhanced swing differential Colpitts voltage-controlled oscillator is presented. The threshold voltage of the MOSFET can be reduced with the body bias technique to lower the supply voltage. The negative conductance boosting technique is used in the cross-coupled pair. The same negative conductance can be obtained but using smaller bias current compared to the conventional Colpitts oscillators. The power consumption is reduced as a result. Moreover, the inductors are placed between the supply voltage and ground. Therefore, the output swing is enlarged. It can both meet the requirement of the mixer and improve the phase noise. The measured frequency tuning range is from 3.73 GHz to 3.79 GHz with the power level from -4 dBm to -2 dBm. The phase noise at 1 MHz offset frequency is -112.3 dBc/Hz. The power consumption is 3.5 mW under a 0.8 V supply voltage. The chip size is 0.972 mm2. And then, the above mentioned mixer and VCO are integrated to be a cascade 8 GHz self-oscillating subharmonic mixer. A buffer is added between the mixer and VCO to avoid the frequency pulling of VCO. The measured conversion gain is 0 dB which is much different from the simulated one of 8.4 dB. Because there is no pad for the VCO output in the layout, the accurate output power of VCO cannot be obtained. The reason might come from the abnormal function of the buffer or low output power of VCO. The measured P1dB and IIP3 are -17 dBm and -5.1 dBm, respectively. With a 0.8 V supply voltage, the power consumption is 3.5 mW. The chip size is 2.06 mm2. Finally, an RF front-end integrating a low noise amplifier, an active balun, a mixer, and a VCO for GPS application into a single chip is presented. The cascode LNA with an active balun produces a differential path to the mixer. The mixer is stacked above the VCO with current reused as a self-oscillating to save the power. The switched transconductance topology is adopted to obtain low voltage operation and low noise. In addition, the mixer core is biased at the moderate inversion mode to reduce the power. The negative conductance boosting technique is also used in the VCO. The switching current source is added to improve the phase noise. The power consumption is 6.7 mW under a 0.8 V supply voltage. The measured conversion gain and noise figure are 13.3 dB and 7.3 dB, respectively. P1dB and IIP3 are -23 dBm and -13.8 dBm. The frequency tuning range is from 1.6 GHz to 1.67 GHz. The phase noise at 1 MHz offset frequency is -108 dBc/Hz. The chip size is 2.4 mm2. From the simulation and measurement results, the proposed four RF sub-circuits have low power consumption and good performance with a low supply voltage. The proposed works are suitable to wireless RF receivers.