| Summary: | 碩士 === 國立中山大學 === 電機工程學系研究所 === 101 === In this thesis, we propose four types non-classical CMOS inverters which the load use junctionless and punch-through technology. These inverters all use traditional NMOS as the driver. And the loads are junctionless PMOS transistor, gate P+-I-P+ transistor, gate P-P-P+ transistor and two embedded oxide punch-through NMOS transistor respectively. For the front of three loads, they use junctionless theory to complete. When apply in CMOS inverter, our proposed can achieve simple fabrication process and low power consumption. Our inverter which composed of NMOS and junctionless PMOS, gate P-P-P+ transistor can reduce 8.38% and 6% delay time compare with traditional SOI CMOS. We also find our inverters which composed of NMOS and gate P+-I-P+ transistor, gate P-P-P+ transistor can decrease 34.2% and 41.5% power consumption respectively and reduce 38.1% delay power product. Our proposed CMOS can improve characteristic and apply in low power circuit.
For the two embedded oxide punch-through CMOS inverter, we use 3D fold up structure that can reduce nearly half layout area compare with traditional CMOS. And we use punch-through mechanism and embedded oxide to achieve all electron for transmission. So our proposed can reduce 84.3% and 80.2% delay time and decrease 59.1% and 33.6% delay power product compare with traditional CMOS and planar unipolar CMOS. We therefore believe that apply in high fast and high packing density circuit is good choice for the future.
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