| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 101 === This thesis presents a 12-bit 100KS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. The A/D converter is designed in TSMC 0.18um CMOS process and operates at a supply voltage of 1.8V. The SAR A/D converter includes track-and-hold (T/H) stage, comparator, digital-to-analog converter and SAR control logic. Bootstrapped switch is used in S/H for improving circuit linearity and reducing the signal distortion. The comparator is composed of a dynamic latched regenerative circuit which gives comparator output better accuracy and higher speed because of positive feedback. Split capacitor array is used in D/A converter to decrease the total capacitance and save average power. Finally, the SAR control logic circuit uses a form of shift-registers-control conversion process and a row of D flip-flops for controlling the spilt capacitor array.
The performance of the converter would be degraded due to the process variation and device mismatches. This thesis proposes self-correction circuits for comparator and D/A separately capacitor array calibration, larger LSB is chosen as a new reference unit capacitor, and produce a new binary-weighted capacitor array by charge redistribution. After D/A calibration, comparator input offset voltage needs to be calibrated and canceled. Because this offset is not linear, a new calibration method is proposed that divides input voltage into multiple windows and use piecewise linear approximation to predict and reduce input offset. Before normal operation, calibration mode is created to do DAC and comparator calibrations. Digital calibration codes are saved in latches, and these digital codes can be used in normal operation mode without wasting other clock cycles. After digital calibration, when sampling rate is 100KS/s, the SNDR is found to be 66.78dB, and ENOB is 10.8 bits. DNL and INL are found to be 0.69 and 0.86 LSB, respectively.
Comparing to other calibration methods, the proposed calibration can predict and reduce offset for full range input voltages, thus has higher accuracy than other digital calibration methods. Since the digital calibration is used, calibration results are saved in flipflops and can be reused repeatedly. Smaller chip and shorter normal mode operation can be achieved. In addition, digital circuit is easier to scale and thus needs smaller area for advanced technologies.
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