Design of CMOS 5.7GHz Receiver Front-end Integrated Circuits

• Main Authors: Chi-Hsiang HSU, 徐麒翔
• Other Authors: Mei-Ling Yeh
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/64514369134523395834

碩士 === 國立臺灣海洋大學 === 電機工程學系 === 101 === In this thesis, we research the receiver front-end circuits for unlicensed WiMAX applications which include low noise amplifier (LNA), voltage-controlled oscillator (VCO) and mixer. The proposed circuits are simulated with the Agilent Advanced Design System (ADS) software supported by National Chip Implementation Center (CIC), and are implemented in TSMC 0.18um 1P6M CMOS process. The first chip is a low noise amplifier (LNA) which uses the cascade architecture and inductive source degeneration to improve linearity. The measurement results show that the power gain is 13.2dB, the input reflection is -30.5dB, the output reflection is -20dB, the P1dB is -13dBm, the IIP3 is -7.5dBm, and the noise figure is 3.49dB. The power consumption is 3.8mW at 1V power supply. The chip size is 0.815*0.683mm2. The second chip is a voltage-controlled oscillator (VCO) which adopts the CMOS structure to include the advantages of PMOS and NMOS. According to the simulation results, the tuning range is 13.4%, the output power is -2.4dBm, the phase noise is -113.7dBc/Hz at 1MHz offset, the figure of merit (FOM) is -191 dBc/Hz, and the power consumption is 0.58mW at 1V power supply. The chip size is 0.8564*0.5982mm2. The last chip is a mixer. In order to get a better power consumption, we use the single-balanced structure and the diode connected load at voltage input. The simulation results show that the RF port reflection coefficient is -27.6dB, LO port reflection coefficient is -25.4dB, IF port reflection coefficient is -27.7dB, the conversion gain is 5.4dB, the IIP3 is -6.8dBm, the P1dB is -16.7dBm, the noise figure is 16dB, and the power consumption is 4.87mW at 1V power supply. The chip size is 0.8872*1.022 mm2. Keywords : WiMAX, LNA, VCO, MIXER