| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 101 === Due to the progress in technology, device size and power consumption keep scaling down. Moreover, more and more function blocks are integrated in a single chip. However, there are also some non-ideal effects accompanied with the progressing CMOS technology. Analog devices suffer from the degrading characteristic such as decreasing supply voltage and increasing leakage current. Thus, it is a tendency that using digital circuits to replace analog circuits.
The 2.4-GHz industrial, scientific and medical (ISM) band is utilized by various short-range wireless systems such as WLAN, Bluetooth and Zigbee. Recently, phase-locked loops (PLLs) are widely used in wireless and wireline communication. As mentioned above, all-digital phase-locked loops (ADPLLs) are more suitable for advanced technology. Thus, this thesis presents an all-digital phase-locked loop with low power time-to-digital (TDC) converter.
The design is analyzed and modeled first, than the implantation is presented. Finally, the chip is fabricated in the TSMC 0.18 μm CMOS technology. The power consumption of TDC is reduced 66%. The measured phase noise are -114 dBc/Hz and -118 dBc/Hz at 1 MHz and 10 MHz offset, respectively and the rms jitter is 0.64 ps. The power consumption is 14.1 mW from 1.8 V supply voltage.
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