The Design and Analysis of a Shifted-Averaging VCO-Based Delta-Sigma Modulator
碩士 === 國立臺灣大學 === 電子工程學研究所 === 101 === This thesis presents a third-order continuous-time delta-sigma modulator with a VCO-based quantizer. A VCO-based quantizer possesses attractive characters of open-loop first-order noise-shaping and barrel-shifting output code when used as closed-loop. However,...
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| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/04289667595917128353 |
| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 101 === This thesis presents a third-order continuous-time delta-sigma modulator with a VCO-based quantizer. A VCO-based quantizer possesses attractive characters of open-loop first-order noise-shaping and barrel-shifting output code when used as closed-loop. However, the non-linear nature of the voltage-to-frequency tuning curve is still a problem to be solved. A shifted-averaging linearization technique is proposed and a modulator with the proposed technique is fabricated in TSMC N65 GP+ 1P6M technology. Aside from the linearization technique, the feed-forward voltage summer and excess loop delay compensation are both integrated into the VCO quantizer, which saves power and area. The prototype modulator is operated at 1.6GHz sampling clock. It achieves peak SNDR of 65.2dB and peak SFDR of 75.4dB within 20MHz bandwidth. The chip dissipates 21.1mW from a 1.2V supply. The active area of this modulator occupies only 0.159mm2.
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