| Summary: | 碩士 === 國立臺灣大學 === 電信工程學研究所 === 101 === In the modern semiconductor industry, it has become harder to keep following Moore’s law, which states that the number of transistors in Integrated Circuit (IC) doubles approximately every two years. Thus, instead of just shrinking the device, several other ways have been proposed to keep up with Moore’s law. Three-dimensional Integrated Circuit (3D IC) has provided a solution by vertically stacking the multiple ICs and thus increased the density of transistors without shrinking it. Within this technology, Through-Silicon Vias (TSVs) are formed in each IC in order to connect the signals vertically. However, because of the typical high density of 105 ~ 107 per cm2, the vertical parallel nature in geometry, and the coupling properties of semiconductor substrate, the equivalent model extraction and performance analysis for TSVs have become time consuming.
This thesis proposes a new extraction method, while including the semiconductor effect, to accelerate the construction of equivalent model with the cylindrical basis, taking advantage of the cylindrical nature of TSVs, while remaining a good accuracy.
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