| Summary: | 碩士 === 國立臺灣大學 === 電信工程學研究所 === 101 === In recent years, with the popularization of mobile phones and wireless network, the RF system has been successfully integrated into human life. The market demand for compact wireless products pushes IC designers to move forward to highly integrated RF system chips. However, with the increasing complexity in the circuit design, process variation problem in every part of the circuits should be considered carefully. The best situation would be every circuit block of RFIC to have the automatic calibration ability, making its specification fit the original designers’ circuit plan and then confirm the chips work properly.
With wireless communication developing rapidly, many outstanding RFIC designs have been found in many references in the field of CMOS system chips, most of which are open-loop design. This kind of design manual makes circuits affected by process variation very easily, which is unfavorable to produce numerously. Therefore, designers should make CMOS RF system able to really apply on many traditional analog circuits. For example, closed-loop design occupies in the most of LPF and PLL architecture, so are many op-based circuits. Designers usually use resistor or capacitor ratios to propose some characteristics of the circuits. Because the error of mismatch between resistors is much lower than process variation, which may get up to 20%. With proper use of ratio relation for circuit implementation, designers can ensure that performance of circuits will not flow too much, highly degrading the probability for circuits to be out of work.
In chapter 3, a gain control technique with a novel amplitude detector for RF amplifiers is presented. By monolithically integrating the amplitude detectors and the differential difference amplifier, the voltage gain of the device under test (DUT) can be controlled by using closed-loop design. Based on the measurement results, there are 8 gain modes with 1-dB resolution in this proposed architecture.
In chapter 4, a programmable-gain RF amplifier is presented. With SAR algorithm, the gain of RF amplifier can be precisely controlled. The control circuit contains amplitude detectors, a comparator, a SAR controller and a DAC. There are 8 gain modes with 1-dB resolution in this proposed architecture. Depend on the measurement results, gain errors in every gain mode are less than 0.5dB.
In chapter 5, a 3-GHz phase shifter with automatic control mechanism is presented. With SAR DLL operation, the phase difference of phase shifter can be precisely controlled. There are 8 phase difference modes with 22.5° resolution in this proposed architecture. Depend on the simulation results, phase difference errors in every mode are less than 2°
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