| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 101 === NAND flash memory has advanced along with the wave of consumer electronics and embedded systems, because of its advantages of non-volatility, lower-power consumption, faster access, and shock-resistance. In recent decades, SSDs (Solid-State Drives) which use NAND flash memory have replaced HDDs (Hard-Disk Drives) in many applications. However, NAND flash memory that has special characteristics (e.g., unsymmetrical operations, out-place updates and, erase limitation) could have performance impacts on SSDs. Currently, the internal architecture of a SSD needs multiple controllers to handle and manage NAND flash chips. However, one controller is in charge of some specific NAND flash chips on its own bus and can’t access other NAND flash chips that owned by other controllers. We call the situation as the bus constraint. The bus constraint will reduce the controllers’ execution parallelism when multiple requests will access those chips on the same bus. To overcome this problem, we will propose a parallel multi-controller design (PMCD) in this thesis. We will implement PMCD and the traditional multi-controller design (TMCD) on an FPGA-based development board (i.e., Altera DE2). According to our experimental results, PMCD can increase about 27.3% performance when compared to TMCD, and the overhead is acceptable.
Keywords: NAND flash memory, Solid-State Drives (SSD) , Controller
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