Highly Extensible and Power-Efficient Self-Timed Magnitude Comparator Architecture

• Main Authors: Liu, Yu-Cheng, 劉祐成
• Other Authors: Yang, Jung-Lin
• Format: Others
• Language: zh-TW
• Published: 102
• Online Access: http://ndltd.ncl.edu.tw/handle/98224593554969425701

碩士 === 南台科技大學 === 電子工程系 === 101 === In the past, comparator is difficult to extensible because the architecture is limited. The equal circuit working time is the longest in comparator, it makes comparator low efficacy. For the reason this paper presents a highly extensible self-timed magnitude comparator architecture. This comparator is constructed with 2, 3 and 4-bit comparator. We substitute their equal circuit by delay-element, beforehand send equal state with adjusting delay time, improve the performance of the comparator, become 2, 3 and 4-bit comparator in new architecture. All of comparator in this paper is asynchronous circuit, it possess robustness and high expandability, not omly applicable asynchronous circuit, but also combine tradition synchronous circuit very simplely. This architecture can build up high efficiency comparator circuit of any bits. In addition to the new architecture improve performance, even can reduce the load in previous circuit. The new 2, 3, 4-bit comparator power consumed lower 24%, 25%, 36% than before. And the new 2-bit comparator speed is 2% slower, but 3, 4-bit the speed is 1.55% and 7% faster.