Mechanism and Improvement of Breakdown Degradation Induced by Interface Charge in UHV Device with P-Top Engineering

• Main Author: MD Imran Siddiqui
• Other Authors: Gene Sheu
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/88820507012314585144

碩士 === 亞洲大學 === 資訊工程學系碩士班 === 101 === In this thesis, describes an innovative p-top engineering to simulate and optimize the breakdown degradations in different regions of the interdigitated layout such as source center (SC), drain center (DC), and flat region of an Ultra high voltage (UHV 800V) device. In manufacturing of UHV device, breakdown voltage degradation takes place due to interface charges, current crowding and breakdown degradation was also observed at wafer-stage with temperature stress resulted from package level reliability tests. Optimizations are done to sustain high breakdown voltage by varying the p-top mask design to investigate the interface charge effect on breakdown. ESD test is also conducted to show the difference in interface charges after stress. A better stability has been obtained for maximum p-top length structure with respect to breakdown and ESD testing. The device characteristics of the LDMOS are simulated after including several physical models, which define the accurate behaviour of the LDMOS. The simulated characteristics are in good agreement with the measured curves, and give together with additional simulations a good insight in the degradation effects of this device. Mesh strategy holds a key in Medici 2D simulations, which has to be taken extra care and needs special type of mesh designing in order to avoid any convergence issues thereafter. This mesh design not only includes eliminating convergence issues, which also emphasize on achieving good doping profile with smooth curves comparatively a better device simulation. Extra care has been taken in drain, source and gate region. Optimized mesh also helps in eliminating unnecessary nodes and overall reduction in number of nodes and results in faster simulation without losing accuracy; this has been presented in this thesis. Keywords: - UHV 800V LDMOS, RESURF, P-Top engineering, TCAD, Interface Charge, HBM, ESD Stress, Breakdown, Specific On-resistance,