Design and Implementation of Radio-Frequency Low-Noise Amplifier and High-Linearity Down-Conversion Mixer

• Main Authors: Yu-Jun Hong, 洪郁鈞
• Other Authors: Yuh-Shyan Hwang
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/npuv7q

碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 101 === This study is to design an ultra-wideband low noise amplifier, a dual-band low noise amplifier, and a high-linearity down-conversion mixer, which are implemented with TSMC 0.18 um CMOS technology and TSMC 90 nm CMOS technology. The first part is a receiver system for ultra-wideband low noise amplifier. It mainly uses the inductive peaking techniques. The first stage circuit uses current reusing technology to increase the circuit gain. The second stage amplifier is based on the traditional resistive shunt feedback amplifier and adds two inductors. Gate feedback inductor resonates with parasitic capacitor (Cgs) of MOSFET to reduce the noise figure. The additional inductor increases high frequency gain and gain flatness. Using this technique, the circuit maximum gain is 9.61dB, -3dB bandwidth is 0.5 ~ 6GHz, noise figure is less than 6.5dB, input third order intercept point (IIP3) is about -11dBm, DC power consumption is 9.5mW, and chip area is 1.04 mm2. The second part is a study of dual-band low noise amplifier, which can be applied to both 2.4 and 5.2 GHz bands. In order to achieve concurrent dual-band characteristics, we use two poles matching at input terminal and use inductive capacitors in series and parallel resonance at output terminal to achieve the dual-band simultaneously match. Since the matching mode of the output terminal, the maximum gain of the circuit will be limited. To overcome this problem, we use a method without increasing power consumption to improve dual-band low noise amplifier gain. The maximum gain of the proposed circuit is 12.9 and 8.2 dB, noise figure is 3.7 and 3.7 dB, input third-order harmonic cutoff point is about -4 and -1dBm, DC power consumption is 7.8mW, and the chip area is 1.13mm2. Finally, we have completed a high-linearity down-conversion mixer using TSMC 90 nm CMOS process. In 4G LTE transmitter, we need a high-linearity quadrature demodulator. Therefore, in the design of quadrature demodulator, we improved the traditional Gilbert mixer. The proposed mixer has gain control functions. When the mixer is in low gain mode, it can increase the linearity of the circuit. In switch stage (LO), the MOSFETs operate in subthreshold region, which can reduce power consumption. The maximum conversion gain is 6.93dB, input third order harmonic intercept point is 5dBm, power consumption is 5.02mW, and the chip area is 0.95 mm2. The quadrature demodulator uses high-linearity down-conversion mixers. Simulation results show that the amplitude error is less than 0.1dB, the phase error is less than 0.5 degree, and the power consumption is 10mW.