CMOS Cascode LC VCO
碩士 === 國立雲林科技大學 === 電子與光電工程研究所碩士班 === 101 === This letter presents a complementary metal-oxide-semiconductor (CMOS) LC voltage controlled oscillator (LC-VCO) using cascode technology. The cascode architecture is implemented with negative conductor circuit for improving phase noise performance in 0.1...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/43382792488429000332 |
| Summary: | 碩士 === 國立雲林科技大學 === 電子與光電工程研究所碩士班 === 101 === This letter presents a complementary metal-oxide-semiconductor (CMOS) LC voltage controlled oscillator (LC-VCO) using cascode technology. The cascode architecture is implemented with negative conductor circuit for improving phase noise performance in 0.18um CMOS process. The post-layout simulation phase noise is -119.6dBc/Hz at the offset frequency of 1Mhz. A total tuning range of 950MHz (from 9.29GHz to 10.24GHz) is achieved as the tuning voltage ranging from 0V to 1.8V. At 1.8V power supply voltage, the total power dissipation is 6.7mW in the core circuit. The cascode LC-VCO exhibited an output power of around -10dBm, leading to a figure of merit (FOM) of 191.45 dBc/Hz, and the core chip area is 330μm × 615μm.
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