CMOS Building Blocks Design for GHz Phase-Locked Loops

• Main Authors: Chao-Yuan Su, 蘇昭源
• Other Authors: none
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/41505508972887326545

碩士 === 國立雲林科技大學 === 電子與光電工程研究所碩士班 === 101 === A high-speed CMOS 1/2 frequency divider is presented. Using fewer transistors and only N-type MOS transistors in the regenerative circuits of the latches, the frequency divider achieves higher speed through the reduced capacitances at the output nodes and transconductance. The goal of device sizing is to achieve highest possible frequency operation. The frequency divider post-layout simulation achieves maximum input frequency of 5.2GHz. The average power consumption of this frequency divider is 3.59mW, and the active area is 128μm×130μm. It is suitable for high-speed operation, while consuming a moderate amount of average power. A multi-GHz LC Voltage-Controlled Oscillator is studied and implemented in 0.18μm CMOS process. The output frequency is tunable from 3.8GHz to 4.8GHz, and the simulation output phase noise are -118dBc/Hz~-113dBc/Hz at 1MHz offset frequency. The power consumption and chip area of the VCO are 6.4mW and 751.13μm×286.5μm, respectively. Lastly, a CMOS Phase/Frequency Detector (PFD) is also described input/output waveforms and I/O characteristics of the PFD are shown.