All-Digital High Speed Wide-Range Linear Cyclic Binary Detection Pulse Width Locked Loops

• Main Authors: Zim-min Hong, 洪子閔
• Other Authors: none
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/01534836448466432599

碩士 === 國立雲林科技大學 === 電子與光電工程研究所碩士班 === 101 === In the high-speed system chip inside, because the internal clock signal transistor manufacturing process, temperature, voltage variations caused by clock signal distortion, and even circuit performance can not be improved or operational error. These show the clock signal pulsewidth stability, in the circuit requirements are also increasing, as in piping systems, high-speed dynamic circuits, double sampling system or need negative edge trigger circuit needs to have stable a pulsewidth. Therefore, a stable working cycle lockout circuit is now an important issue. This thesis presents a new fully digital pulsewidth control circuit, using a linear cyclic delay line used in this thesis proposed a linear cyclic binary pulse detector and pulse generator mechanism so that the circuit does not need to increase the delay line progression to the low operational frequency state. The proposed linear cyclic binary pulse detectors, delay line design is only sixteen stage, in a linear cycle technology, and special arrangements are arranged in ascending binary mode. The proposed pulse detection circuit that can detect linear continuous, rapid quantized pulse code and cycle detection code detect quantitative takes only three clock cycles to complete. In this thesis, the pulse generator for the two-stage delay line architecture, when operated at high frequency band, close the loop delay line, only four bit from low to generate pulsewidth controlled delay line multiplexer. When operating in low frequencies, the open loop delay line, a linear binary cycle, generate a lot of low-frequency output pulse required delay time. In this thesis is unbalanced delay error compensation circuit is proposed in order to self-calibration techniques, through the pulse code subtractor correction techniques detect only feedback correction twice to reach locked output clock. In this thesis, the performance of the proposed new architecture using TSMC 90nm CMOS analog, with 25%, 50%, 75% three output locked pulse width is available, the operating bandwidth of 100MHz ∼ 3GHz, lock time of 25 clock cycles.