Low Power Consumption and High Linearity Mixer Design for DSRC Applications

• Main Authors: Chih-Wen Huang, 黃志文
• Other Authors: Chien-Chang Huang
• Format: Others
• Language: zh-TW
• Online Access: http://ndltd.ncl.edu.tw/handle/46582160162133920335

碩士 === 元智大學 === 通訊工程學系 === 101 === This paper presents a low power consumption and high linearity mixer design for dedicated-short-range-communications (DSRC) applications. The designed mixer is in the double-balanced configuration similar to the Gilbert-cell structure, The mixer core is worked at the triode region to perform the resistive mixing for better noise figure and linearity, the local oscillator (LO) signal is applied to the bulk and the source terminals in order to use the bulk-injection method to reduce the required LO power and dc power consumption. In the down-convert mode, the measured conversion loss and input 1-dB compression point are about 16.26 dB and 1.5 dBm, the input third-order intercept point (IP3) of 13 dBm, the noise figure and power consumption are about 15.41 dB and 0.16 mW; in the up-convert mode, the measured conversion loss is about 18.53 dB, the input and output 1-dB compression point are about -4.5 dBm and -13 dBm, the input and output IP3 are about -3 dBm and -7 dBm.