An All-digital Delay-locked Loop for 3D ICs Die-to-die Clock Synchronization

• Main Authors: Chi-Yu Hou, 侯紀宇
• Other Authors: Ching-Che Chung
• Format: Others
• Language: en_US
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/js9kwd

碩士 === 國立中正大學 === 資訊工程研究所 === 102 === With the advance of system-on-a-chip (SoC) technology, many transistors can be integrated into a single chip. However, in an SoC, there may have many global wires with long distances, and the highest clock speed of a SoC are usually limited by these wires. Therefore, the through silicon via (TSV) technology is proposed to shorten the length of the global wires. Besides, according to the Moore’s Law, the (TSV) technology becomes more and more popular in recent years with the increasing of the integrated transistors in a single chip. However, the TSV delay variation phenomenon during manufacturing may cause the SoC systems not work correctly. The TSV delay variation problem affects the data transmission between chips. Therefore, the clock signals between chips need to be phase aligned to simplify the data transmission between chips. Hence, two all-digital delay-locked loops (ADDLLs) with architectures are proposed in this thesis to synchronize the clock signals between two chips. The proposed ADDLLs are implemented in TSMC 90nm CMOS process with standard cells, and they can tolerate PVT variations. Besides, the first ADDLL architecture with two TSV channels can compensate for the TSV delay variation with the digital controlled varactor-based delay line. The second ADDLL architecture can avoid the TSV delay variation problem with only a single TSV channel. The first ADDLL with two TSVs can operate with the input frequency range from 300MHz to 1GHz, and the maximum phase error is 21.9ps. The second ADDLL with a single TSV can operate with the input frequency range from 200MHz to 1GHz, and the maximum phase error is 80ps.