An All-digital Delay-locked Loop for 3D ICs Die-to-die Clock Synchronization
碩士 === 國立中正大學 === 資訊工程研究所 === 102 === With the advance of system-on-a-chip (SoC) technology, many transistors can be integrated into a single chip. However, in an SoC, there may have many global wires with long distances, and the highest clock speed of a SoC are usually limited by these wires. There...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/js9kwd |