Variable-Length VLIW Encoding for TI C64x DSP Processors

• Main Authors: Bo-Yu Su, 蘇柏宇
• Other Authors: Tay-Jyi Lin
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/6ea586

碩士 === 國立中正大學 === 資訊工程研究所 === 102 === VLIW architecture has been demonstrated in various types of embedded system applications such as: signal, image, audio processing, more traditional superscalar, RISC architecture provides better performance and lower design costs. But code compiled will often include many NOP instructions, which occur because there is not enough ILP to completely fill an execute packet with useful instructions, leading to its program size relative to other architectures than many high. TI C64x is one of the most successful VLIW DSP, although the application NOP Removal but the use of fixed-length instructions and only for high-performance, there are still too large for the size of the program in question. The study found that the instruction encoding, such as: (1) conditional execution, (2) registers, (3) immediate value, (4) function code etc. field some bits are not used in execute, so we proposed variable length instruction encoding, and adaptive instruction grouping & dispersal scheme (CAP), a fixed-length instruction bundle integrated variable-length instruction VLIW encoding, and then analysis the proportion of valid bits & used in various fields for C64 and complete instructions encoding to achieve the purpose of improving instruction encoding density. We also propose decompression hardware architecture and consideration for each method of analysis overhead. Finally this paper discusses delay and hardware complexity of the front in C64 pipeline when using our approach. In this thesis, the proposed method for C64 when instruction parallelism is not high still can reach 74 to 84 percent of the instruction compression ratio, and only about 2ns delay in the instruction decoding.