Length-constrained Escape Routing of Differential Pairs

• Main Authors: Yi-Hsun Hsiao, 蕭義勳
• Other Authors: Jin-Tai Yan
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/07812599471679013782

碩士 === 中華大學 === 資訊工程學系碩士在職專班 === 102 === As the feature size of microelectronic technology becomes smaller, modern electronic systems become larger and more complicated. The number of integrated circuit(IC) increased in printed circuit board(PCB), IC and IC circuit lines between more density. Due to most of the ball grid array(BGA) package IC is the number of high pin, board-level routing works becomes more difficult in PCB designs. A differential pair(DP) is used to transmit high-speed signal in high-frequency digital circuit, a DP becomes an important technique for modern PCB designs. In this paper, given a set of DPs inside a single chip and the maximum tolerant length difference in a DP. Based on the of the observation of the DP escape routing result from industrial boards, all the DPs can be divided into local and global DPs. By using a two-phase routing approach, direct escape routing for local DPs in first phase, firstly, the merging grids of all the DPs can be selected to satisfy the given length constraint. Furthermore, some local differential pairs can be escaped and routed by using direct escape paths. Escape routing for global DPs in second phase, firstly, the feasible merging grids of all the DPs can be selected to satisfy the given length constraint. Furthermore, the global DPs can be escaped and routed by using obstacle-aware flow-based escape paths. Compared with Yan’s network-flow-based approach[11], the experimental results show that our proposed approach reduces 79.6% of CPU time on the average to achieve 100% escape routability for six tested examples. Additionally, our proposed approach can be obtained length-constrained escape routing results under small length constraint for the tested example in reasonable CPU time.