| Summary: | 碩士 === 大葉大學 === 機械與自動化工程學系 === 102 === Along with the Internet fast growth, the topic of network security is valued more and more.Before having never carried on any safe mechanism to handle, the data all is delivered with clear statement(plain text) in the network upper-class.The data at this time is to don't be taken up a post what protection, as long as you have a whichever person to pick these encapsulations down, then know the data content of transport.
For the sake of the concealed of the protection data, many mechanisms that add a decryption are in succession put forth.Be widely been adoptive most among them, for several decades of and should be FIPS Standard(DES) of Encryption of 46-3 Data for drawing up in PUB.But due to the progress of computer operation capability, airtight key length only DES of 56 bits the safety of the algorithm has already been queried.Consequently there is the creation of the algorithm of Advanced Encryption Standard(AES).
This text makes use of Altera the FPGA platform of the company carry out AES to encrypt/decryption algorithm, look back the theories back ground of AES first, configure in the text, the convert of round gold key, and creation and plait of gold key decoding process and immediately after introduce opposite should of the electric circuit configure a design.This text with ALTERA Stratix the chips of the II EPS60 F1020 C5 imitate and get the highest the 90.03 MHzs of clock rate as a result, AES-128, AES-192 and AES-256 can be outputted a result in 21, 24, 29 Clocks respectively, throughput reduction of a fraction don't be 548.75 Mbpses, 480.16 Mbpses, 397.37 Mbpses, and integrate complete AES-128, 192, 256 it adding and decrypting electric circuit, can make the encryption handled to satisfy the velocity request of the broadband times.
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