| Summary: | 碩士 === 逢甲大學 === 電子工程學系 === 102 === This paper applies to achieve active noise cancellation chip design for high-fidelity in-ear earphones, respectively; using NLMS (Normalization Least Mean Square) and LMS algorithm in the structure are pipelined computation by ANC_a type and sequential input by ANC_b of two architectures. Both architectures are improved dual-microphone feed-forward architecture before, respectively improved computing algorithms and adding P (z) and S (z) parameters, etc., to complete a single microphone active noise cancellation design. Cost savings on hardware algorithms microphone design. Algorithm designed to reduce the cost of the microphone. Hardware architecture, we add adaptive filtering architecture pipelined architecture to accelerate the iterative calculation speed and reduce the computation time, in order to achieve real-time computing performance; and designs custom memory access large amounts of operational data to FPGA (field programmable gate array) to verify the effect of noise. In chip design, through use of RTL and gate-level power optimization technology, let power-optimized to reduce power consumption and optimize the power consumption of the chip. From the experimental results, the thesis anti-noise algorithm design ANC_b architecture, which can effectively eliminate noise for 325 ~ 875 Hz, 18 dB maximum at 480 Hz to eliminate noise; and in the Core Power, which can effectively reduce power consumption by 2.5%. By using standard Cell-based design flow, using TSMC90nm process has been completed ANC_a chips. This chip can reach a maximum operating frequency of 87.2 MHz, which can effectively eliminate noise for 100 ~ 300 Hz, 10 dB maximum at 175Hz to eliminate noise. From the above results, that the proposed application of the active noise cancellation chip design for high-fidelity in-ear earphones through improved algorithms and architectures can be against external noise can be effectively eliminated.
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