| Summary: | 碩士 === 國立中興大學 === 資訊科學與工程學系 === 102 === Network-on-Chip (NoC) is designed to tackle the architectural scalability and interconnection problems in many-core architectures. Multiple layers are stacked together using through silicon vias (TSV) and establish inter-die connectivity in the 3D integration technology.
In 3D NoC, the congestion problem and the thermal problem are the major issues. Once the congestion problem occurs, the performance of 3D NoC rapidly degrades such as increasing transmission latency, extra power consumption, higher temperature and imbalanced traffic among different logic layers. In addition, the effect of high temperature also increases transmission latency, leakage power, and cooling cost.
In this thesis, an advanced temporary relay routing (ATRR) algorithm is proposed to achieve three goals: (1) collecting the information of congestion and throttling to balance traffic; (2) reducing path diversities (PD) to improve the average latency; (3) adjusting routing paths to dissipate heat in 3D NoC. Simulation results validated by mathematical analysis show that the proposed scheme can improve average latency, approach better heat balance, as well as obtain high scalability.
|
|---|
