Placement Density Aware Power Switch Insertion Algorithm for Power Gating Designs

• Main Authors: Che-ChunLin, 林哲均
• Other Authors: Jai-Ming Lin
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/51230359829462076132

碩士 === 國立成功大學 === 電機工程學系碩士在職專班 === 102 === Due to advance in manufacture technology, leakage current becomes a serious problem in modern IC designs. Power gating is a widely applied technique to resolve this problem, which requires to place power switches into a low-power domain to turn off supply voltage. Insertion of power switches is an important step in power gating designs because number and locations of power switches have great impact on chip area and IR-drop of circuits. Unlike previous works using the greedy algorithm to handle this problem, this thesis proposes a simplified model to approximate the required equivalent resistance of power switches in a low-power domain, and determines proper number and types of power switches based on the value. It also adopts the binary search method to find the precise value. Further, in order to reduce its impact on pre-placed standard cells, a mathematical approach is proposed to determine the locations of these power switches. We compare our method with the work of engineers and the greedy method which was implemented by us based on test cases provided by Himax. Experimental results demonstrate that our approach uses less area of power switches to satisfy the IR-drop constraint. Moreover, our approach has small influence to pre-placed standard cells.