Simulation and Fabrication of Low Capacitance Lateral Transient Voltage Suppressor

• Main Authors: Chin-HunChung, 鍾錦翰
• Other Authors: Wen-Hsi Lee
• Format: Others
• Language: en_US
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/70755053626401957323

碩士 === 國立成功大學 === 電機工程學系 === 102 === Technology advances has shrunk the size of integrated circuits, making portable devices much more available and one of the major class of consumer electronics. However, these IC’s are more vulnerable to Electrostatic Discharge (ESD) hazard, since their reduced dimensions leads to problems such as a more penetrable oxide layer caused by reduced oxide thickness. Lower operating voltage also requires stricter protection devices. Besides, the operating speed of modern devices has increased dramatically. These all sum up to the need of a transient voltage suppressor, or TVS, which is designed to protect the IC’s from ESD and electrical surges with a respond speed that matches the electronics today. In this thesis, the Silvaco TCAD software is used to simulate the fabrication and electric characteristics of a bi-directional lateral TVS. The parameters for the desired characteristics are found through simulation. Tannar L-Edit software is then used to design photo mask and tape-out wafers in FAB for engineer pilot run. Measurement data of the actual device fabricated is collected and compared with the simulation result. The clamping voltage measured is about 7.4V, which is close to the simulation result. The I/O to I/O capacitance is about 0.52pF, while the capacitance between I/O and ground is about 1.073pF. These measured values are different from the ones simulated. The cause to these differences may be the overly simplified calculation for the equivalent capacitance. The packaging material also contributes to the overall capacitance, making the actual value larger than the simulated one.