A Novel Seven-Level Inverter without Electrolytic Capacitor

• Main Authors: Yen-HungWu, 吳彥宏
• Other Authors: Jiann-Fuh Chen
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/07640680840202051927

碩士 === 國立成功大學 === 電機工程學系碩士在職專班 === 102 === In this thesis, a novel single-phase seven-level electrolytic capacitor-less inverter topology is proposed. In conventional inverter topologies, the problems of voltage unbalance of capacitor induce distortion of output voltage. And, the life time of capacitors is shorter than semiconductor components. Due to, the proposed topology which is composed of two transformers can achieve seven multi-level output without electrolytic capacitor. hence, it would not have the question of voltage unbalance of electrolytic capacitors, the longer life time and electric isolation are achieved. The operating principle, mode analysis, control method and modulation method are introduced. Finally, a 220 Vrms / 3 kW laboratory prototype of seven-level inverter with input voltage 300 Vdc is implemented to verify the theoretical analysis and the performance. The control scheme is presented by DSP (Digital Signal Processor ) TMS320F28335.