| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 102 === Power consumption is one of important issues in power constraint applications such as wireless sensor networks (WSN). For these power constraint applications, we need a low power system-on-a-chip (SoC) to extend life time. In breakdown of power consumption, SRAMs are one of major sources of power consumption in the SoC. Scaling supply voltage into near-threshold or sub-threshold region is one of effective techniques to reduce power consumption. However, severe variations may occur in the near-threshold and the sub-threshold region. For a read-decoupled SRAM, read failures may happen because the current ratio between a keeper and a pull-down network has large variations. In this thesis, we propose a local column sensing keeper scheme to detect the variations and adaptively generate a proper keeper current to deal with the read functionality issues. Meanwhile, power consumption is reduced by minimizing the keeper contention current. A test chip is fabricated using TSMC 90nm technology to demonstrate the proposed SRAM. According to post-layout simulation results, the proposed scheme supports near-threshold and sub-threshold operation and achieves 24% power reduction when compared with state-of-the-art designs in the worst leakage case.
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